1. Field of the Invention
This invention relates generally to digital processing, and more particularly to a device for rapidly calculating a discrete numerical convolution.
2. Description of the Prior Art
In the past a distributed arithmetic and read only memory (ROM)-accumulator approach has been suggested for the calculation of the product of a variable factor and a constant factor. In that approach, a table of predetermined partial products is stored, typically in ROMs.
Such an approach lacked flexibility because of the ROM's inability to permit changing or substitution of the constant.
An article by Peled et al, entitled "A New Hardware Realization of Digital Filters", in IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. ASSP-22, No. 6, 1974, describes an approach using distributed arithmetic in a digital filter.
An article by Burrus, entitled "Digital Filter Structures Described by Distributed Arithmetic", in IEEE Transactions on Circuits and Systems, Vol. CAS-24, No. 12, 1977, discloses generally the convolution and distributed arithmetic approach to multiplication.
An article by De Man et al, entitled "High-Speed NMOS Circuits for ROM-Accumulator and Multiplier Type Digital Filters", in the IEEE Journal of Solid-State Circuits, Vol. SC-13, No. 5, Oct. 1978, explores circuit techniques which can lead to full integration of digital filter structures.
The present invention, in addition to providing flexibility in reprogramming the constant multiflier, permits a modular approach to multiplication. Any number of the disclosed modules may be coupled to provide either multiplication of longer bit streams or simultaneous multiplication of a variety of products.